/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
//
// You may copy and modify these files for your own internal use solely with
// Xilinx programmable logic devices and  Xilinx EDK system or create IP
// modules solely for Xilinx programmable logic devices and Xilinx EDK system.
// No rights are granted to distribute any files unless they are distributed in
// Xilinx programmable logic devices.
//
/////////////////////////////////////////////////////////////////////////////////
#warning "Please provide the correct address value for the definition FLASH_IMAGE_BASEADDR." 
#define FLASH_IMAGE_BASEADDR  0x200000

#define LD_MEM_WRITE_ERROR  1
#define LD_SREC_LINE_ERROR  2
#define SREC_PARSE_ERROR    3
#define SREC_CKSUM_ERROR    4

typedef unsigned char   uint8_t;
typedef unsigned short  uint16_t;
typedef unsigned int    uint32_t;

typedef char   int8_t;
typedef short  int16_t;
typedef int    int32_t;


